1. Field of the Invention
Generally, the present disclosure relates to formation of thin films on a substrate. More specifically, the present disclosure relates to formation of thin dielectric films on substrates achieved by using chemical vapor deposition (CVD) techniques. Yet more specifically, the present disclosure is concerned with CVD techniques used during fabrication of microstructure devices, such as integrated circuits and the like.
2. Description of the Related Art
The ongoing trend in electronic towards more and more complex integrated circuits requires the dimensions of electronic devices to decrease, in order to achieve an ever increasing integration density.
Transistors are the dominant circuit elements in current integrated circuits. Currently, several hundred millions of transistors may be provided in presently available complex integrated circuits such as microprocessors, CPUs, storage chips, and the like. It is then crucial that the typical dimensions of the transistors included in an integrated circuit are as small as possible, so as to enable a high integration density.
Among the various fabrication technologies of integrated circuits, the MOS (metal-oxide-semiconductor) technology is currently the most promising approach, since it enables producing devices with superior characteristics in terms of operating speed, power consumption and cost efficiency. The CMOS (complementary metal-oxide-semiconductor) technology is a particular implementation of the MOS technology wherein pairs of complementary field-effect transistors (FETs), i.e., p-channel transistor and an n-channel transistors grouped in pairs, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies.
During the fabrication of complex integrated circuits using CMOS technology, millions of FETs are formed in active regions defined within a semiconductor layer supported by a substrate. An active region is to be understood as an area of the semiconductor layer within which and on top of which a FET is formed.
Presently, the layer in which most integrated circuits are formed is made out of silicon, which can be provided in crystalline, polycrystalline or amorphous form. Other materials such as, for example, dopant atoms or ions may be introduced into the original semiconductor layer.
A MOS transistor or generally a FET, irrespective of whether an n-channel transistor or a p-channel transistor is considered, comprises a source and a drain region, highly doped with dopants of the same species. An inversely or weakly doped channel region is then arranged between the drain and the source regions. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, can be controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region depends, among others, on the mobility of the charge carriers, and on the distance along the transistor width direction between the source and drain regions, which is also referred to as channel length. For example, by reducing the channel length, the channel resistivity decreases. Thus, an increased switching speed and higher drive current capabilities of a transistor can be achieved by decreasing the transistor channel length.
In order to manufacture a transistor, and specifically a FET, a plurality of operations on the semiconductor substrate are carried out including: deposition of layers of different materials, patterning of the deposited layers, etching, ion implantations, surface polishing and planarization, etc.
Film deposition lies at the base of the semiconductor manufacturing process. Therefore, depositing material layers on a semiconductor substrate or on active region surfaces with substantially uniform properties is of a paramount importance for fabricating high-performance electronic devices. It is particularly desirable that the deposited material layers are highly conformal, i.e., that the maximum thickness difference across the whole layer is less then approximately 5%. Ideally, material layers with a uniform thickness all across the substrate are desirable.
Currently, one of the most widespread deposition techniques of thin material layers used in the semiconductor industry is CVD. Since usually highly uniform layers have to be formed, low-pressure CVD (LPCVD) is often preferred to conventional CVD. Reduced pressures tend to reduce undesired gas reactions, thereby improving the layer uniformity across the substrate.
FIG. 1a schematically shows a cross-section of a reaction chamber 150 used for a typical CVD or LPCVD film growth. Before initiating the deposition process, a plurality of substrates 101 is introduced into reaction chamber 150. Substrates 101 may be any carrier appropriate for supporting a semiconductor device. Substrates 101 are usually stacked upon each other along a direction which is parallel to the longitudinal axis of reaction chamber 150.
After inserting substrates 101 into reaction chamber 150, a gaseous ambient is then established inside reaction chamber 150 by using appropriate means (not shown) for maintaining a gas flow 164, 166, 168. Incoming gases 162 can be introduced into reaction chamber 150 through inlets 152. Upon entering reaction chamber 150, gases 162 mainly flow along the direction indicated by arrows 164. A certain amount of incoming gases 162 flows from main flow direction 164 to the surface of substrates 101, as indicated by arrows 166. It should be noticed that the gases in flow directions 166 mainly flow from the edge to the center of substrates 101.
Before starting the deposition, incoming gases 162 typically include an inert species, such as nitrogen (N2) and the like. Deposition is then initiated by adjusting the composition of incoming gases 162 so as to include appropriate reactant gases. The particles of reactant gases 162 reaching the surface of substrates 101 are then absorbed on the surface, subsequently undergoing surface diffusion and chemical reactions with surface species resulting in film formation. The gaseous by-products of the reactions are desorbed from substrates 101 and removed from reaction chamber 150 through a gas outlet 156. The path followed by exhaust gases is approximately represented by arrows 168.
The energy to drive the chemical reactions leading to film formation can be provided in several manners. However, thermal energy is the most frequently provided source of energy.
Reaction chamber 150 shown in FIG. 1a includes four heating elements 154b, 154cb, 154ct and 154t, each of which is designed in order to establish gaseous ambient 164, 166, 168 within reaction chamber 150 at a predetermined, respective process temperature. The four heating elements are stacked upon each other and can be maintained at different temperatures. Thus, heating elements 154b, 154cb, 154ct and 154t divide reaction chamber 150 into four different process temperature zones.
In general, the term “process temperature” should be understood throughout the disclosure as indicating the temperature of the interior of reaction chamber 105, i.e., of heating elements 154b, 154cb, 154ct and 154t, the gases flowing inside reaction chamber 150 and all other components of reaction chamber 150 in contact with the heating elements. With a certain degree of approximation, the process temperature in each zone may be considered to be approximately equal to the temperature of the corresponding heating element. It should be appreciated that the process temperature might not be the temperature of the substrate of surfaces 101, since upon a temperature variation thermal equilibrium might not be fully established across substrates 101.
It is customary to keep the four heating elements at gradually increasing temperatures when moving from bottom heating element 154b to top heating element 154t. For example, the temperature difference between top heating element 154t and bottom heating element 154b could be of approximately 40-50° C. Different temperature zones are established in reaction chamber 150 in order to compensate for the reaction gas depletion when moving from the bottom (closer to gas inlets 152) to the top (farther from gas inlets 152) of reaction chamber 150.
Line 174 shown in FIG. 1b is a plot of the process temperature profile within a region of a reaction chamber as a function of process time during a conventional growth process. Line 174 could for example represent the temperature of one of heating elements 154b, 154cb, 154ct, 154t of reaction chamber 150 shown in FIG. 1a and the region of the reaction chamber could be one of the four temperature zones of reaction chamber 150. During segment 172 of line 170, the reaction chamber temperature is ramped up to a predetermined operation temperature To. As said above, operation temperature To may be different in different areas of the reaction chamber. During temperature ramp-up segment 172 an inert gas, such as N2, may flow in the reaction chamber.
After reaching operation temperature To, this is maintained as indicated by the horizontal segment 174 of line 170. More specifically, first portion 174s of segment 174 indicates a time interval 174st during which the temperature is stabilized across the substrates loaded in the reaction chamber. At the end of time interval 174st, deposition is initiated and continued for a time interval 174dt, as shown by the second portion 174d of segment 174.
After completing the deposition, the process temperature in the reaction temperature is ramped down, as indicated by segment 176 of line 170. The reaction chamber may be purged by allowing an inert gas to flow therein during temperature ramp-down 176. Finally, the substrates can be removed from the reaction chamber.
During deposition, the temperature is substantially homogenous across a given substrate and is approximately equal to operation temperature To. In these conditions, thin layer growth turns out to be inhomogeneous across the substrate surface, resulting in a layer with a greater thickness at the substrate edge and a reduced thickness at the substrate center. Consequently, the grown layer has a characteristic bowl-like shape. This is mainly due to the depletion of reactant gases when flowing from the edge to the center of substrates, for example as indicated by arrows 166 in FIG. 1a. 
When manufacturing semiconductor electronic devices, deposition of conformal thin nitride layers, especially silicon nitride (Si3N4), has in the last decades assumed an increasing importance. Si3N4 is for example used for forming spacer structures on the sidewalls of gate structures, which are particularly crucial circuit elements for protecting sensitive layers included in gate structures formed according to the high-k/metal gate (HKMG) technology. In this case, one or more highly conformal Si3N4 layers are deposited on a semiconductor layer after forming the gate structure. The deposited Si3N4 layers are then patterned in order to assume the desired shape.
One more case for which depositing homogeneous nitride layers is a critical issue is during formation of isolation structures in the device substrate. Isolation structures electrically and spatially isolate neighboring active regions. For current manufacturing technologies, isolation structures are formed by using the so-called shallow trench isolation (STI) technique. Nitride layers are used within the STI techniques as “hard masks” protecting the below-lying active region. Nitride layers are used also as stop layers for chemical mechanical polishing processes carried out in order to remove excess oxide material when forming STI regions.
A typical process flow followed when forming STI structures is schematically illustrated in FIGS. 1c-1h. 
FIG. 1c shows a cross-section of a portion of a substrate 101 for a semiconductor electronic micro-device. A thin oxide film 103, normally called “pad oxide”, has been formed on the surface of substrate 101, for example by means of a thermal growth. The purpose of pad oxide 103 is reducing the stress applied by the above-lying deposited layers to substrate 101.
Subsequently, as shown in FIG. 1d, a deposition 181 is performed in order to form a nitride layer 110, typically Si3N4, on the upper surface of pad oxide 103. Deposition 181 is usually a CVD or LPCVD carried out as described above with reference to FIGS. 1a and 1b. When forming nitride (Si3N4) layer 110 shown in FIG. 1d, the reactant gases 162 introduced into reaction chamber 150 shown in FIG. 1a normally include ammonia (NH3) and dichlorosilane (SiH2Cl2). Again with reference to FIG. 1d, nitride layer 110 has normally a thickness greater than approximately 70 nm. For advanced semiconductor manufacturing technologies such as the 45-nm or 28-nm technologies, the thickness of nitride layer 110 can be of approximately 80 nm.
Thereafter, nitride layer 110 is patterned in order to form a hard mask with openings in predetermined points of the layer exposing the surface of substrate 101. Openings are positioned above the substrate areas in which the STI structures are to be formed. Patterning of nitride layer 110 usually involves a photolithographic process wherein a pattern is formed on a photoresist deposited on the surface on the surface of nitride layer 110. Pattern formation in the photoresist is then followed by an etching process performed in order to transfer the pattern onto the nitride layer 110.
After forming the hard mask in nitride layer 110, an appropriate etching process is carried out in order to form trenches in substrate 101. FIG. 1e shows that, after completing this substrate etch, trenches 101t are formed in substrate 101 in correspondence to the apertures 110a in nitride layer 110.
As shown in FIG. 1f, trenches 101t are filled with a dielectric material, which is typically the same oxide 103 as that initially grown on the surface of substrate 101. If the surface of substrate 101 is comprised of silicon, then oxide 103 may advantageously be silicon dioxide (SiO2).
After depositing oxide 103 in order to fill trenches 101t, the excess material is removed, typically by using chemical mechanical polishing (CMP). FIG. 1g shows the system after performing excess material removal. During CMP, nitride layer 110 acts as an etch-stop layer.
Finally, nitride layer 110 is removed and STI structures 103sti are formed as shown in FIG. 1h. Active regions (not shown) can subsequently be formed on opposite sides of STI structure 103sti. 
As shown in FIG. 1h, STI structure 103sti forms a step on the surface of substrate 101 having a height 103g. This step is generated due to the presence of nitride layer 110 during the CMP performed so as to remove the excess oxide material and described with reference to FIG. 1g. Consequently, the step height 103g is nearly equal or slightly less than the thickness of nitride layer 110 in the vicinity of STI structure 103sti. 
It is desirable that the steps formed by STI structures 103sti have as uniform as possible a height 103g across the entire surface of substrate 101. In order for this step height homogeneity to be achieved, it is crucial that the thickness of nitride layer 110 is uniform across the whole substrate 101.
Thus, a nitride layer 110 formed by means of a conventional deposition process as described above with reference to FIGS. 1a and 1b is not a satisfactory solution. As said above, during a conventional LPCVD process, reactant gases are normally depleted when flowing from the edge towards to center of a substrate. This results in a bowl-like shape of the deposited layer, i.e., a layer with a significantly larger thickness on the substrate edge than in the center. For example, the thickness difference of a deposited layer can be up to about 2 nm, for substrates positioned in the upper part of the reaction chamber farther away from the reactant gas inlets.
Several strategies have been implemented in the state of the art in order to contrast the reactant gas depletion towards the substrate center. Most of these strategies involve a temperature tilt across the substrate surface.
U.S. Pat. No. 6,461,979 proposes a solution consisting in ramping down the temperature in the reaction chamber during deposition. Although applicable to relatively short deposition times (less than 10-15 min), this solution cannot conveniently be pursued when longer deposition times (about 50 min or greater) are required, such as when depositing a nitride layer to be used as a hard mask during STI structure formation. For longer deposition times, a continuous temperature decrease would bring the reaction chamber temperature below the lower threshold of the process window for the nitride process well before the deposition ends. The process window is the range of process temperatures within which nitride deposition can be effectively carried out. When the process temperature decreases below the lower threshold of the process window, the deposition rate is reduced down to an excessively low value.
An alternative method is proposed by U.S. Pat. No. 6,537,677, which allows one to run a deposition above the lower threshold of the temperature process window. The proposed method consists of dividing the deposition into several stages, with the temperature being ramped down during each stage. Between consecutive ramping-down stages the temperature is to be increased while the deposition is interrupted. This solution is not satisfactory, since it requires a much longer process time due to the regular disruptions of the deposition process. This results in a lower throughput of the semiconductor device manufacturing process.
A further deposition method, described in U.S. Patent Application Publication No. 2009/0246371, relies on overheating the reaction chamber before starting the deposition in order to induce a temperature gradient across the substrate. Nitride deposition is carried out at a constant process temperature after the overheating. This method can be conveniently applied when forming relatively thin (approximately 10 nm) nitride layers, thus using short deposition times (approximately 15 min). However, when thicker (about 80 nm) nitride layers and longer deposition times (approximately 50 min) are required, this method fails to achieve its goals. This is mainly due to the fact that the temperature gradient across the substrate vanishes within the first stage of the deposition process (initial approximately 15 min), thus causing the subsequent second deposition stage (final approximately 35 min) to be run with a substantially homogeneous temperature across the substrate. Thus, during the second deposition stage the gas depletion from the edge to the center of the substrate cannot be compensated for by any temperature gradient. This causes the layer thickness to increase at the substrate edge with respect to the thickness in the substrate center during the second deposition stage, thereby finally resulting in a bowl-shaped deposited layer.
Yet other solutions could be envisaged in order to improve the uniformity of a nitride layer thickness upon deposition.
For example, one could run the deposition process with a double pitch boat load, in order for the larger spacing between consecutive substrates in the reaction chamber to considerably reduce gas depletion across the substrate. This solution is not satisfactory since it reduces the throughput by 50%.
Alternatively, the pressure during deposition could be reduced, so as to improve in-substrate uniformity. This solution entails the disadvantage of requiring a much longer deposition time, thereby also resulting in a reduced throughput.
In view of the drawbacks and disadvantages of the solutions known from the state of the art, there is a need for an improved method of growing material layers on a substrate surface with homogeneous properties, in particular with a homogeneous thickness. This need is particularly felt for nitride layers with a thickness greater than approximately 50 nm.